On-chip RF isolation techniques

被引：47

作者：

Blalack, T ^{[1
]}

Leclercq, Y ^{[1
]}

Yue, CP ^{[1
]}

机构：

[1] Cadence Design Syst, San Jose, CA 95134 USA

来源：

PROCEEDINGS OF THE 2002 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING | 2002年

关键词：

D O I：

10.1109/BIPOL.2002.1042919

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

On-chip isolation is a function of many interdependent variables. This paper uses industry examples to highlight isolation impacts of technology substrate doping levels and triple wells, grounding / guard rings, shielding, capacitive decoupling, and package inductance.

引用

页码：205 / 211

页数：7

共 9 条

[1]

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[2]

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[3]

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[4]

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[5]

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[6]

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[7]

TAKESHITA T, 2002, IEEE INT SOL STAT CI, V45, P258

[8]

VANZEIJL PTM, 2002, IEEE INT SOLID STATE, V45, P86

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Yue, CP ;

Wong, SS .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (05) :743-752

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