Digital implementation of cellular sensor-computers

被引：19

作者：

Foeldesy, Peter

Zarandy, Akos

Rekeczky, Csaba

Roska, Tamas

机构：

[1] Hungarian Acad Sci, Anal & Neural Comp Lab, H-1111 Budapest, Hungary

[2] Catholic Univ, Jedlik Labs, Fac Informat Technol, Budapest, Hungary

[3] Eutecus Inc, Berkeley, CA USA

来源：

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | 2006年 / 34卷 / 04期

关键词：

focal plane; sensor-processor; parallel processing; SIMD; CMOS sensor; CNN-UM;

D O I：

10.1002/cta.367

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A bit-sliced digital implementation method of the cellular sensor-computer is proposed. The proposed sensor-computer architecture is analysed, and an implementation example is introduced. The analogue and the digital implementation methods are compared. It is found that on or below 0.18 mu m technology the digital implementation of the cellular sensor-computer is a viable alternative to the analogue versions in general-purpose designs. Copyright (C) 2006 John Wiley & Sons, Ltd.

引用

页码：409 / 428

页数：20

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