UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect

被引：9

作者：

Fukasaku, K ^{[1
]}

Ono, A ^{[1
]}

Hirai, T ^{[1
]}

Yasuda, Y ^{[1
]}

Okada, N ^{[1
]}

Koyama, S ^{[1
]}

Tamura, T ^{[1
]}

Yamada, Y ^{[1
]}

Nakata, T ^{[1
]}

Yamana, M ^{[1
]}

Ikezawa, N ^{[1
]}

Matsuda, T ^{[1
]}

Arita, K ^{[1
]}

Nambu, H ^{[1
]}

Nishizawa, A ^{[1
]}

Nakabeppu, K ^{[1
]}

Nakamura, N ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Div, Sagamihara, Kanagawa 2291198, Japan

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015389

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, Over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the requirement for various performance, multi-V-TH, multi-thickness gate-oxide process, low-leakage gate dielectric are incorporated in FEOL. To suppress RC increase compared to previous generation, low-k (Keff=3.1) interlayer dielectric and Cu interconnect dual damascene are incorporated in BEOL.

引用

页码：64 / 65

页数：2

共 5 条

[1]

Boeuf F., 2001, IEDM, P637

[2]

HUANG SF, 2001, IEDM, P237

[3] CMOS device optimization for system-on-a-chip applications [J].

Imai, K ;

Yamaguchi, K ;

Kudo, T ;

Kimizuka, N ;

Onishi, H ;

Ono, A ;

Nakahara, Y ;

Goto, Y ;

Noda, K ;

Masuoka, S ;

Ito, S ;

Matsui, K ;

Ando, K ;

Ohashi, EHT ;

Oda, N ;

Yokoyama, K ;

Takewaki, T ;

Sone, S ;

Horiuchi, T .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :455-458

[4]

ONO A, 2001, IEDM, P511

[5]

YU B, 2001, IEDM, P937, DOI DOI 10.1109/IEDM.2001.979669

← 1 →