CMOS device optimization for system-on-a-chip applications

被引：18

作者：

Imai, K ^{[1
]}

Yamaguchi, K ^{[1
]}

Kudo, T ^{[1
]}

Kimizuka, N ^{[1
]}

Onishi, H ^{[1
]}

Ono, A ^{[1
]}

Nakahara, Y ^{[1
]}

Goto, Y ^{[1
]}

Noda, K ^{[1
]}

Masuoka, S ^{[1
]}

Ito, S ^{[1
]}

Matsui, K ^{[1
]}

Ando, K ^{[1
]}

Ohashi, EHT ^{[1
]}

Oda, N ^{[1
]}

Yokoyama, K ^{[1
]}

Takewaki, T ^{[1
]}

Sone, S ^{[1
]}

Horiuchi, T ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Div, Sagamihara, Kanagawa 2291198, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904354

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 0.13-muM-generation CMOS technology optimized for system-on-a-chip (SoC) applications. The wide-range of performances obtained using a triple gate oxide and multiple threshold voltage control allows the SoC to operate at high speed with low standby power. Core CMOS transistors, which have a 1.9-nm gate oxide and a 95-nm physical gate length, show an excellent drive current of 740/335 muA/mum at 1.2 V. Low-power CMOS transistors have a standby current of only 2-0.2 pA/muM with a 2.6-nm gate oxide and a 120-nm gate length. This technology has also been used to make a 1.4-mum(2) loadless 4T SRAM cell as well as a 2.5-mum(2) 6T cell. The wiring RC delay has been reduced by integrating Cu interconnects with a low-k "Ladder-oxide" layer.

引用

页码：455 / 458

页数：4

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