A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip

被引：12

作者：

Goto, Y ^{[1
]}

Imai, K ^{[1
]}

Hasegawa, E ^{[1
]}

Ohashi, T ^{[1
]}

Kimizuka, N ^{[1
]}

Toda, T ^{[1
]}

Hamanaka, N ^{[1
]}

Horiuchi, T ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Lab, Sagamihara, Kanagawa 2291198, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852804

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have developed a triple gate oxide CMOS technology that integrates 0.10-mu m gate length 1.2-V highspeed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.

引用

页码：148 / 149

页数：2

共 5 条

[1]

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Guarin, F ;

Crabbe, E ;

Su, L .

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[3]

IMAI K, 1999, S VLSI TECH, P51

[4]

Luan H. F., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P141, DOI 10.1109/IEDM.1999.823865

[5]

1999, INT TECHNOLOGY ROADM, P86

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