Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al2O3 Gate Dielectric

被引:16
作者
Cheng, Chao-Ching [1 ]
Chien, Chao-Hsin [2 ,3 ,4 ]
Luo, Guang-Li [4 ]
Lin, Ching-Lun [1 ]
Chen, Hung-Sen [1 ]
Liu, Jun-Cheng [1 ]
Kei, Chi-Chung [5 ]
Hsiao, Chien-Nan [5 ]
Chang, Chun-Yen [1 ]
机构
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan
[2] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
[3] Natl Chiao Tung Univ, Inst Elect Engn, Hsinchu 300, Taiwan
[4] Natl Nano Device Labs, Hsinchu 300, Taiwan
[5] Natl Appl Res Labs, Instrument Technol Res Ctr, Hsinchu 300, Taiwan
关键词
Al2O3; forming gas annealing (FGA); gate-last metal-oxide-semiconductor field-effect transistor (MOSFET); germanium; high-k gate dielectrics; junction diode; LEAKAGE CURRENT; GERMANIUM; DIFFUSION; SILICON; IMPLANTATION; PASSIVATION; TEMPERATURE; ACTIVATION; IMPACT; AL2O3;
D O I
10.1109/TED.2009.2023948
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al2O3/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V-1 . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V-1 . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
引用
收藏
页码:1681 / 1689
页数:9
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