The scaling challenges of CMOS and the impact on high-density non-volatile memories

被引：4

作者：

Baldi, L. ^{[1
]}

Bez, Roberto ^{[1
]}

机构：

[1] Front End Technol & Mfg, STMicroelect, I-20041 Agrate Brianza, Italy

来源：

MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS | 2007年 / 13卷 / 02期

关键词：

Parasitic Capacitance; Flash Memory; Technology Node; NAND Flash; NAND Flash Memory;

D O I：

10.1007/s00542-006-0157-4

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Solid-state mass storage has experienced recently an explosive growth, mainly related to digital consumer application (digital cameras, MP3 players, USB keys). The demand is not expected to slow down in the near future. Present storage technology is based on NAND Flash, and it appears that there is still margin to scale it down at least to the 45 nm node. The likely appearance of physical limits to scalability is pushing for the investigation of alternative storage technologies, and several solutions have been proposed. However, any kind of memory needs a selection mechanism, and related parasitic effects can be a severe limitation to scaling. Scaling challenges of select devices (mostly CMOS), and their impact on memory scaling will be investigated, and alternatives proposed.

引用

页码：133 / 138

页数：6

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