共 122 条
[2]
Åberg I, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P52
[3]
[Anonymous], 2006, 2006 INT EL DEV M IE, DOI DOI 10.1109/IEDM.2006.346810
[4]
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell
[J].
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST,
2004,
:657-660
[5]
DEFORMATION POTENTIALS AND MOBILITIES IN NON-POLAR CRYSTALS
[J].
PHYSICAL REVIEW,
1950, 80 (01)
:72-80
[6]
Bastard G., 1992, Wave Mechanics Applied to Semiconductor Heterostructures
[7]
Bir G. L., 1974, Symmetry and Strain-Induced Effects in Semiconductors
[9]
Chan V, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P77
[10]
Chau R, 2005, COMP SEMICOND INTEGR, P17

