A Combined Study of p- and n-Channel MOS Devices to Investigate the Energetic Distribution of Oxide Traps After NBTI

The aim of this paper is to highlight the effect of gate bias switches and charge pumping (CP) on oxide trap and interface-state recovery. In general, variations in gate bias correspond to shifts of the Fermi level (E-F) across the silicon band gap and trigger carrier exchange between stress-induced oxide traps and the silicon substrate. Our measurements strongly indicate that interface-state recovery is accelerated by the CP measurement itself, whereas oxide-trap occupation can be controlled more efficiently by slow Fermi level switches. Oxide-trap neutralization/charging by electron/hole capture works similarly to interface states but with larger time constants indicating inelastic carrier tunneling between the silicon substrate and stress-induced donor-like oxide traps. In a combined study, we compare threshold voltage shifts and recovery of identically processed NMOS and PMOS devices which allows us to gain access to the full silicon band gap by appropriate gate biasing. Additional CP measurements on identically stressed reference devices allow us furthermore to differentiate quantitatively between interface-state and oxide-trap contributions. Finally, by referring oxide-trap-dependent V-TH shifts after stress to certain gate voltages during recovery, energetic profiling of oxide traps with respect to the Fermi level position becomes possible.