100Gbit/s optical clock recovery using electrical phaselocked loop consisting of commercially available components

被引：24

作者：

Phillips, ID ^{[1
]}

Ellis, AD ^{[1
]}

Widdowson, T ^{[1
]}

Nesset, D ^{[1
]}

Kelly, AE ^{[1
]}

Trommer, D ^{[1
]}

机构：

[1] BT Labs, Ipswich IP5 3RE, Suffolk, England

来源：

ELECTRONICS LETTERS | 2000年 / 36卷 / 07期

关键词：

D O I：

10.1049/el:20000506

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Polarisation and wavelength insensitive 100Gbit/s optical clock recovery using an electrical phaselocked loop consisting entirely of commercially available components is demonstrated. The system exhibits excellent long-term stability, with a timing jitter of similar to 250fs.

引用

收藏

页码：650 / 652

页数：3

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