20GBIT/S DR BASED TIMING RECOVERY CIRCUIT

被引：8

作者：

MONTEIRO, P

MATOS, JN

GAMEIRO, A

DAROCHA, JRF

机构：

[1] Department of Electronics and Telecommunications, University of Aveiro

来源：

ELECTRONICS LETTERS | 1994年 / 30卷 / 10期

关键词：

CLOCK RECOVERY; DIELECTRIC RESONATORS; OPTICAL COMMUNICATION;

D O I：

10.1049/el:19940518

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates.

引用

页码：799 / 800

页数：2

共 4 条

[1] STATISTICAL PROPERTIES OF TIMING JITTER IN A PAM TIMING RECOVERY SCHEME [J].