Noise-aware interconnect power optimization in domino logic synthesis

被引:8
作者
Kim, KW [1 ]
Jung, SO
Narayanan, U
Liu, CL
Kang, SM
机构
[1] Brocade Commun Syst Inc, San Jose, CA 95110 USA
[2] T RAM Inc, San Jose, CA 95134 USA
[3] Intel Corp, Santa Clara, CA 95052 USA
[4] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 30043, Taiwan
[5] Univ Calif Santa Cruz, Baskin Sch Engn, Santa Cruz, CA 95064 USA
关键词
domino logic; dual threshold voltage; keeper transister; logic synthesis; power optimization; threshold voltage; transister sizing;
D O I
10.1109/TVLSI.2002.801630
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.
引用
收藏
页码:79 / 89
页数:11
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