A multichip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity

被引：87

作者：

Chicca, Elisabetta ^{[1
]}

Whatley, Adrian M.

Lichtsteiner, Patrick

Dante, Vittorio

Delbruck, Tobias

Del Giudice, Paolo

Douglas, Rodney J.

Indiveri, Giacomo

机构：

[1] Univ Zurich, Inst Neuroinformat, CH-8057 Zurich, Switzerland

[2] ETH, Swiss Fed Inst Technol, CH-8092 Zurich, Switzerland

[3] Italian Natl Inst Hlth, I-00161 Rome, Italy

[4] Natl Inst Nucl Phys, I-00185 Rome, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2007年 / 54卷 / 05期

关键词：

address event representation (AER); asynchronous; cooperative-competitive; neural chips; neural networks; neuromorphic; orientation tuning; peripheral component interconnect (PCI)-AER; VLSI; winner take all (WTA);

D O I：

10.1109/TCSI.2007.893509

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons.

引用

页码：981 / 993

页数：13

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