Effects of denudation anneal of silicon wafer on the characteristics of ultra large-scale integration devices

被引:5
作者
Cho, WJ
Kuwano, H
机构
[1] Hyundai MicroElect Ltd, Proc Dev Team, Hungduk Ku, Cheongju 361480, South Korea
[2] Keio Univ, Fac Sci & Technol, Dept Elect Engn, Kohoku Ku, Yokohama, Kanagawa 223, Japan
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2000年 / 39卷 / 6A期
关键词
denudation anneals; junction leakage; gate-oxide breakdown; bulk microdefects; refresh time;
D O I
10.1143/JJAP.39.3277
中图分类号
O59 [应用物理学];
学科分类号
摘要
The effectiveness of denudation annealing at high temperatures on the characteristics of ultra large-scale integration (ULSI) devices has been studied. The secondary-ion mass spectroscopy (SIMS) profile showed that the oxygen atoms near the wafer surface diffuse out during the denudation anneal and the amount of outdiffused oxygen atoms increases with the increase of denudation annealing temperature. The depth of the defect-free zone (DFZ) at the surface region, the breakdown property of the thin gate oxide of 7 nm thickness and the leakage current of PN junction diodes were greatly improved following by the denudation annealing process at a high temperature. It is found that the refresh properties of a 256 Mbit dynamic random-access memory (256 M-DRAMs) were closely related to the depth of the DFZ at the device surface and were improved by the denudation annealing. Therefore, denudation annealing at high temperatures is effective for the fabrication of reliable quarter-micron level DRAM devices.
引用
收藏
页码:3277 / 3280
页数:4
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