Characterization and modeling of hysteresis phenomena in high K dielectrics

被引：115

作者：

Leroux, C ^{[1
]}

Mitard, J ^{[1
]}

Ghibaudo, G ^{[1
]}

Garros, X ^{[1
]}

Reimbold, G ^{[1
]}

Guillaumot, B ^{[1
]}

Martin, F ^{[1
]}

机构：

[1] CEA, LETI, D2NT, F-38054 Grenoble 9, France

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419276

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An original technique for the dynamic analysis of Id(Vg) hysteresis on high K stacks is proposed, allowing the characterization of Vt shift transients at short times. The experimental results demonstrate that trapping/de-trapping mechanism by tunneling from the substrate must be considered. Furthermore, a new model based on a trap-like approach is successfully developed to interpret the dependence of hysteresis phenomena with high k gate stack architecture.

引用

页码：737 / 740

页数：4

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