A 250MHz-2GHz wide range delay-locked loop

被引：3

作者：

Kim, BG ^{[1
]}

Kim, LS ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept EECS, Taejon 305701, South Korea

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358758

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a wide range delay-locked loop (DLL) for a synchronous clocking to support a dynamic frequency and voltage scaling. The DLL achieves wide range by using multiple phases from its variable delay line. A phase detector is proposed to increase the locking speed and alleviate the phase offset owing to the inherent mismatch of the charge pump. The DLL achieves the static phase error under 10ps. At 1 GHz, its RMS jitter and peak-to-peak jitter are 1.57ps and 10.7ps respectively.

引用

页码：139 / 142

页数：4

共 4 条

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[3]

XANTHOPOULOS T, 2001, IEEE INT SOL STAT CI, P402

[4]

Yoshimura T., 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), P66, DOI 10.1109/VLSIC.1998.688006

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