Active GHz clock network using distributed PLLs

被引：53

作者：

Gutnik, V ^{[1
]}

Chandrakasan, AP ^{[1
]}

机构：

[1] MIT, Microsyst Technol Lab, Cambridge, MA 02139 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 11期

关键词：

clock network; multiple oscillator system; phase-locked loop;

D O I：

10.1109/4.881199

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested, Undesirable large-signal stable (mode-locked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. A 16-oscillator 1,3-GHz distributed clock network in 0.35-mum CMOS is presented here.

引用

页码：1553 / 1560

页数：8

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