SRAM variability and supply voltage scaling challenges

被引：12

作者：

Kapre, R. ^{[1
]}

Shakeri, K. ^{[1
]}

Puchner, H. ^{[1
]}

Tandigan, J. ^{[1
]}

Nigam, T. ^{[1
]}

Jang, K. ^{[1
]}

Reddy, M. V. R. ^{[1
]}

Lakshminarayanan, S. ^{[1
]}

Sajoto, D. ^{[1
]}

Whately, M. ^{[1
]}

机构：

[1] Cypress Semicond Inc, 195 Champion Court, San Jose, CA 95134 USA

来源：

2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL | 2007年

关键词：

SRAM; cell stability; NBTI;

D O I：

10.1109/RELPHY.2007.369863

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have developed a methodology for SRAM cell design that unifies all the major design criterion - cell stability, write margin, read speed and leakage into a single metric. This metric has been used to design a 65nm cell while accounting for challenges posed by increased Vt variability, Vcc scaling and NBTI drift. The impact of NBTI drift on the periphery of a high speed SRAM has been simulated and measured.

引用

页码：23 / +

页数：2

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