Wireless baseband digital signal processing

被引：45

作者：

Zhang, H ^{[1
]}

Prabhu, V

George, V

Wan, M

Benes, M

Abnous, A

Rabaey, JM

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94704 USA

[2] Myricom Inc, Arcadia, CA 91006 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 11期

关键词：

digital signal processors; energy conservation; field-programmable gate arrays; reconfigurable architectures; speech coders; wireless;

D O I：

10.1109/4.881217

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm x 6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-mum 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network.

引用

页码：1697 / 1704

页数：8

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