A 1-mbit MRAM based on 1T1MTJ bit-cell integrated with copper interconnects

被引：105

作者：

Durlam, M ^{[1
]}

Naji, PJ ^{[1
]}

Omair, A ^{[1
]}

DeHerrera, M ^{[1
]}

Calder, J ^{[1
]}

Slaughter, JM ^{[1
]}

Engel, BN ^{[1
]}

Rizzo, ND ^{[1
]}

Grynkewich, G ^{[1
]}

Butcher, B ^{[1
]}

Tracy, C ^{[1
]}

Smith, K ^{[1
]}

Kyler, KW ^{[1
]}

Ren, JJ ^{[1
]}

Molla, JA ^{[1
]}

Feil, WA ^{[1
]}

Williams, RG ^{[1
]}

Tehrani, S ^{[1
]}

机构：

[1] Motorola Inc, Tempe, AZ 85284 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 05期

关键词：

magnetic tunnel junction (MTJ); magnetoresistance ratio (MR); magnetoresistive RAM (MRAM);

D O I：

10.1109/JSSC.2003.810048

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm(2) 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-mum CMOS process utilizing five layers of metal and two layers of poly.

引用

页码：769 / 773

页数：5

共 4 条

[1]

[Anonymous], 2001, ISSCC FEBR

[2]

Durlan M., 2000, ISSCC, P130

[3]

SCHEUERLEIN R, 2002, IEEE INT SOL STAT CI, P128

[4] Recent developments in Magnetic Tunnel Junction MRAM [J].

Tehrani, S ;

Engel, B ;

Slaughter, JM ;

Chen, E ;

DeHerrera, M ;

Durlam, M ;

Naji, P ;

Whig, R ;

Janesky, J ;

Calder, J .

IEEE TRANSACTIONS ON MAGNETICS, 2000, 36 (05) :2752-2757

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