Dual-metal gate technology for deep-submicron CMOS transistors

被引：57

作者：

Lu, Q ^{[1
]}

Yee, YC ^{[1
]}

Ranade, P ^{[1
]}

Takeuchi, H ^{[1
]}

King, TJ ^{[1
]}

Hu, CM ^{[1
]}

Song, SC ^{[1
]}

Luan, HF ^{[1
]}

Kwong, DL ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852774

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Dual-metal gate CMOS devices with rapid-thermal chemical-vapor deposited (RTCVD) Si3N4 gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO2. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

引用

页码：72 / 73

页数：2

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