0.42 μm contacted pitch dual damascene copper interconnect for 0.15 μm EDRAM using tapered via aligned to trench

被引：3

作者：

Hattori, T ^{[1
]}

Masuda, H ^{[1
]}

Sato, H ^{[1
]}

Matsuda, T ^{[1
]}

Yamamoto, A ^{[1
]}

Kato, Y ^{[1
]}

Ogawa, S ^{[1
]}

Ohsaki, A ^{[1
]}

Ueda, T ^{[1
]}

机构：

[1] Matsushita Elect Ind Co Ltd, ULSI Proc Technol Dev Ctr, Minami Ku, Kyoto 6018423, Japan

来源：

PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2000年

关键词：

D O I：

10.1109/IITC.2000.854310

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A tapered via aligned to a trench without any expanding of trench width for 0.42 mu m contacted pitch dual damascene Cu interconnect has been studied. Cu via filling and via electrical properties were dependent on shapes of vias, and it has been found that the aligned tapered via has advantages for the fine pitch Cu dual damascene interconnect.

引用

页码：155 / 157

页数：3

共 4 条

[1] Full copper wiring in a sub-0.25 μm CMOS ULSI technology
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Heidenreich, J
Goldblatt, R
Cote, W
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McDevitt, T
Motsiff, W
Simon, A
Dukovic, J
Wachnik, R
Rathore, H
Schulz, R
Su, L
Luce, S
Slattery, J
[J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 773 - 776
[2] Fukuda T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P619, DOI 10.1109/IEDM.1999.824229
[3] Iguchi M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P615, DOI 10.1109/IEDM.1999.824228
[4] 1999, ITRS, P167

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