Advanced IC packaging for the future applications

被引:17
作者
Anjoh, I [1 ]
Nishimura, A
Eguchi, S
机构
[1] Hitachi Ltd, Semicond & IC Div, Tokyo 187, Japan
[2] Hitachi Ltd, Hitachi Res Labs, Tokyo 187, Japan
关键词
ball grid array (EGA); chip scale package (CSP); lead on chip (LOG); package;
D O I
10.1109/16.661237
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The performance of electronic equipment is improving rapidly, Portable electronic equipment requires smaller and thinner packaging systems for saving space and miniaturization. In addition, highly integrated, high-speed applications demand improved electrical performance to minimize noise effects, As a result of these considerations, the role of IC packaging has expanded from its traditional role of protecting the integrity and performance of an IC, to being a central factor in the. development of electronic system concepts, In developing the optimum system, packaging technology must be a prime design consideration to ensure optimum performance, reliability, and cost, Soldering technology and Printed Wiring Board (PWB) routing density are two of the major technological issues facing miniaturized packaging systems today, Chip Scale Package (CSP), which is a new concept in packaging technology has been introduced, This is an ideal technology to enable the design and manufacture of the next generation of electronic equipment, while overcoming many of the technological issues facing system development.
引用
收藏
页码:743 / 752
页数:10
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