A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

被引：46

作者：

Zhang, K ^{[1
]}

Bhattacharya, U ^{[1
]}

Chen, Z ^{[1
]}

Hamzaoglu, F ^{[1
]}

Murray, D ^{[1
]}

Vallepalli, N ^{[1
]}

Wang, Y ^{[1
]}

Zheng, B ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346592

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 mum(2) 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.

引用

页码：294 / 295

页数：2

共 5 条

[1] A pico-joule class, 1 GHz, 32 KByte x 64b DSP SRAM with self reverse bias [J].

Bhavnagarwala, AJ ;

Kosonocky, SV ;

Immediato, M ;

Knebel, D ;

Haen, AM .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :251-252

[2]

KIM K, 1998, VLSI TECH S DIG, P68

[3]

Maiz J, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P519

[4] A fully synchronized, pipelined, and re-configurable 50Mb SRAM on 90nm CMOS technology for logic applications [J].

Zhang, K ;

Bhattacharya, U ;

Ma, L ;

Ng, Y ;

Zheng, B ;

Bohr, M ;

Thompson, S .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :253-254

[5] The scaling of data sensing schemes for high speed cache design in sub-0.18μm technologies [J].

Zhang, K ;

Hose, K ;

De, V ;

Senyk, B .

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2000, :226-227

← 1 →