Ultra low stress and low temperature patternable silicone materials for applications within microelectronics

With the introduction of new low-k dielectric materials into the mainstream 90 nm tech node it is anticipated that reduced yields will occur if adequate materials and packaging methodologies are not employed in the back-end of line. A silicone under the bump approach is discussed to improve solder joint reliability reducing the strain. Methodologies are discussed for successful processing and integrating patternable silicones using both stencil printable (thickness 50170 mum) and photopatternable silicones (thickness 6-50 mum). (C) 2004 Elsevier B.V. All rights reserved.