An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration

Silicone Under the. Bump (SUB) is a novel wafer level packaging (WLP) concept aimed at improving the reliability of solder joints. Poor reliability of the solder joints is attributed to large stresses generated by a mismatch between the thermal expansion coefficient of the chip and that,of the printed circuit board. The severity of this problem increases with chip size. The SUB is integrated into the package between the chip and solder joint. Improvement in the solder joint reliability on thermal Cycling results from dissipation of the stresses into the low modulus silicone layer. Non-linear 3D Finite Element Analysis (FEA) has been used to predict the reliability of a model package under thermal cycling. The model incorporates a SUB design with the electrical interconnect layer partially covering the silicone. Simulation with a virtual design of experiment has been performed to assess the sensitivity of the models design, parameters to the induced plastic strain in the solder and metallization. These parameters include the metal lead configuration, the geometry of the SUB and the material properties of the SUB., The magnitude of the thermal cycling damage was represented,by an increment of the equivalent plastic strain in each metallization layer and solder joint. The results suggest that using a narrow metallization strip on the SUB significantly reduces damage to the solder. However, fatigue damage to the metallization then becomes the critical parameter for reliability. An optimal design based on a compromise between solder joint and metallization reliability is proposed.