A 16Mb MRAM featuring bootstrapped write drivers

被引：32

作者：

DeBrosse, J ^{[1
]}

Arndt, C ^{[1
]}

Barwin, C ^{[1
]}

Bette, A ^{[1
]}

Gogl, D ^{[1
]}

Gow, E ^{[1
]}

Hoenigschmid, H ^{[1
]}

Lammers, S ^{[1
]}

Lamorey, M ^{[1
]}

Lu, Y ^{[1
]}

Maffitt, T ^{[1
]}

Maloney, K ^{[1
]}

Obermeyer, W ^{[1
]}

Sturm, A ^{[1
]}

Viehmann, H ^{[1
]}

Willmott, D ^{[1
]}

Wood, M ^{[1
]}

Gallagher, WJ ^{[1
]}

Mueller, G ^{[1
]}

Sitaram, AR ^{[1
]}

机构：

[1] IBM Microelect Div, Essex Jct, VT 05452 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

16Mb; MRAM; 1T1MTJ; memory; cell; architecture; bootstrap and driver;

D O I：

10.1109/VLSIC.2004.1346648

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 16Mb Magnetic Random Access Memory (MRAM) is demonstrated in 0.18mum three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42mum(2) 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) cell, measures 79mm(2) and features a x16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.

引用

页码：454 / 457

页数：4

共 5 条

[1]

BETTE A, 2003, S VLSI CIRC

[2]

Durlam M, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P995

[3] A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects [J].

Durlam, M ;

Naji, P ;

Omair, A ;

DeHerrera, M ;

Calder, J ;

Slaughter, JM ;

Engel, B ;

Rizzo, N ;

Grynkewich, G ;

Butcher, B ;

Tracy, C ;

Smith, K ;

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Ren, J ;

Molla, J ;

Feil, B ;

Williams, R ;

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2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2002, :158-161

[4]

SITARAM AR, 2003, S VLSI TECHN, P15

[5]

WORLEDGE D, UNPUB MAGNETIC PHASE

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