Fully self-aligned tri-layer a-Si:H thin-film transistors with deposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFT's with deposited n(+) contacts. Since no critical data alignment is required, this sample process is well suited to fabrication of short channel TFT's. We have fabricated fully self-aligned tri-layer a-Si:H TFT's with excellent device performance, and contact overlaps <1 mu m. For a 20-mu channel length TFT with an a-Si:H thickness of 13 nm. the linear region (V-DS = 0.1 V) and saturation region (V-DS = 25 V) extrinsic mobility values are both 1.2 cm(2)/V-s, the off currents are <1 pA, and the on/off current ratio is >10(7).