Two dimensional optical interconnect between CMOS IC's

The main reason for the expected I/O-bottleneck in future data processing systems, is the increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. It is generally perceived that the number and the difficulty of the technical challenges continue to increase as technology moves forward, as pointed out in the 1999 SIA Roadmap. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion, EMI) result in an increasing mismatch between silicon processing capabilities and interconnect performance, pushing packaging costs and required effort to significantly higher levels. Due to the envisaged importance for IC development well within the next decade, optoelectronic interconnects have been chosen as a subject of focused proactive research, an initiative called "Advanced reseach initiative in microelectronics: optoelectronic interconnects for integrated circuits", (MEL-ARI-OPTO Cluster(1)). In the framework of this initiative, Optical I/O over the entire chip area is pursued as a possible solution to these interconnection problems in the project OIIC2 ("Optically Interconnected Integrated Circuits"). The central issue of OIIC concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers high-throughput data interconnects on inter-chip and Multi-chip Module (MCM) level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator, implementing state-of-the-art technology, and two link demonstrators, aiming at a high speed approach with 16 channels (Gigalink), and a low power, high density approach on 100 mu m pitch with 100 channels (Photonlink). In the paper, progress and results in the project on architecture, components, optical pathways and mounting techniques for the system demonstrator will be highlighted. This system demonstrator aims at using a smart-pixel like interconnect structure to create a logically S-dimensional architecture, conceptually consisting; of a number of electronic planes (electrical FPGAs), that are interconnected bidirectionally along a regular pattern that runs across the chip surface. The full-custom CMOS FPGA circuit is an 8 x 8 array of simple configurable logic blocks (a 4-bit function table, one flipflop), interconnected by a programmable 6 x 6 switch matrix fabric, including the access to off-chip optical interconnections. The optical components consist of two 8 x 8 source arrays (either LEDs or VCSELs) and two 8 x 8 InP detector arrays, which are flip-chip bonded to the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving and receiving circuits are realised in CMOS, and are intermixed with the digital circuits. Each of the 256 optical channels is designed to operate at an information rate of 80 Mbit/s, a typical data rate for high-end commercial FPGAs. To ensure reliable communication over so many parallel channels in a noisy digital environment, AC-coupled communication with Manchester coded data is used in the design. The optical pathways between the central chip and its two neighbours consists of removable 8 x 16 Plastic Optical Fiber (POF) ribbons. The two outer chips are equipped with 2 x (8 x 8) ribbons with horizontal insertion POF-ribbon connectors allowing a closed, toroidal interconnect, or an open optical I/O access to the system. Preliminary tests of the CMOS functionality have been completed with good results. A methodology for hybrid assembly, packaging and passive alignment of all components has been implemented. The hybridisation and packaging steps of the CMOS chips and the optical components, final assembly and measurements will be discussed.