Digital circuit applications of resonant tunneling devices

被引:331
作者
Mazumder, P [1 ]
Kulkarni, S [1 ]
Bhattacharya, M [1 ]
Sun, JP [1 ]
Haddad, GI [1 ]
机构
[1] Univ Michigan, Dept Elect Engn & Comp Sci, Solid State Elect Lab, Ctr High Frequency Microelect, Ann Arbor, MI 48109 USA
基金
美国国家科学基金会;
关键词
logic circuits; multivalued logic circuits; negative resistance circuits; resonant tunneling devices;
D O I
10.1109/5.663544
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling,, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD + HBT and RTD + MODFET gates are described that provide a single-gate, self-latching MAJORITY function in addition to basic NAND, NOR, and inverter gates. This forms the basis for design of high-speed nanopipelined 32- and 64-bit adders using only a single 4-bit adder block. A 32-bit nanopipelined correlator, designed using RTD + HBT logic, demonstrates a simulated power-delay product of 32 pJ while achieving a simulated throughput of one 32-bit correlation every 100 ps. Examples of multiple-valued logic circuits using resonant tunneling devices are presented, which achieve significant compaction in terms of device count over comparable binary logic circuits in conventional technologies. These include a four-valued 4:1 multiplexer using four RTD's and 21 HBT's, a mask programmable four-valued single-input gate using four RTD's and 14 HBT's, and a four-step countdown circuit using one RTD and three HBT's.
引用
收藏
页码:664 / 686
页数:23
相关论文
共 69 条
[21]   THE BOUND-STATE RESONANT TUNNELING TRANSISTOR (BSRTT) - FABRICATION, DC IV CHARACTERISTICS AND HIGH-FREQUENCY PROPERTIES [J].
HADDAD, GI ;
REDDY, UK ;
SUN, JP ;
MAINS, RK .
SUPERLATTICES AND MICROSTRUCTURES, 1990, 7 (04) :369-374
[22]  
Haddad GI, 1996, 1996 EIGHTH INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, P129
[23]  
HANYU T, 1993, IEICE T ELECTRON, VE76C, P1126
[24]  
HAYES JP, 1988, COMPUTR ARCHITECTURE
[25]  
HSU PYT, 1985, P 12 INT S COMP ARCH, P28
[26]  
Imamura K., 1991, JEE (Journal of Electronic Engineering), V28, P76
[27]  
KAMEYAMA M, 1990, PROCEEDINGS OF THE TWENTIETH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, P355, DOI 10.1109/ISMVL.1990.122647
[28]   DESIGN AND IMPLEMENTATION OF QUATERNARY NMOS INTEGRATED-CIRCUITS FOR PIPELINED IMAGE-PROCESSING [J].
KAMEYAMA, M ;
HANYU, T ;
HIGUCHI, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (01) :20-27
[29]  
KULKARNI S, 1995, P INT C INT MICR SPA, P157
[30]   MULTIPLE-VALUED COUNTER [J].
KUO, TH ;
LIN, HC ;
POTTER, RC ;
SCHUPE, D .
IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (01) :106-109