A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency.