Compact distributed RLC interconnect models - Part I: Single line transient, time delay, and overshoot expressions

Novel compact expressions that describe the transient response of a high-speed distributed resistance, inductance, and capacitance (rlc) interconnect are rigorously derived with on-chip global interconnect boundary conditions. Simplified expressions enable physical insight and accurate estimation of transient response, time delay, and overshoot for high-speed global interconnects with the inclusion of inductance.