CMOS PLL calibration techniques

被引:42
作者
Aktas, A
Ismail, M
机构
[1] Analog VLSI Lab, Ohio State University, Columbus, OH
来源
IEEE CIRCUITS & DEVICES | 2004年 / 20卷 / 05期
关键词
D O I
10.1109/MCD.2004.1343243
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Phase lock loops (PLLs) serve as frequency synthesizers in fully integrated radios targeting future generations of broadband wireless applications. These PLLs use wideband voltage-controlled oscillators (VCOs) covering a wide tuning range. There are two approaches to calibrate the tuning range of a wideband VCO in a PLL operation. One approach is to apply the digital control word externally and the other is the auto calibration of the digital control word with a PLL calibration circuit. A third new technique is proposed. The new method searches TRIM codes starting from the highest TRIM code toward to find desired code which satisfies the required VCO control voltage. The proposed method is implemented in a WLAN frequency synthesizer.
引用
收藏
页码:6 / 11
页数:6
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