Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics

被引：45

作者：

Shanware, A ^{[1
]}

Visokay, MR ^{[1
]}

Chambers, JJ ^{[1
]}

Rotondaro, ALP ^{[1
]}

Bu, H ^{[1
]}

Bevan, MJ ^{[1
]}

Khamankar, R ^{[1
]}

Aur, S ^{[1
]}

Nicollian, PE ^{[1
]}

McPherson, J ^{[1
]}

Colombo, L ^{[1
]}

机构：

[1] Texas Instruments Inc, Silicon Technol Dev, Dallas, TX 75243 USA

来源：

41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2003年

关键词：

D O I：

10.1109/RELPHY.2003.1197747

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electrical instability due to charge trapping in high-k materials is a primary concern for the usefulness of these films in future CMOS devices. This paper reports the effect of charge trapping on the threshold voltage and transistor drive current of devices made with HfSiON gate dielectric. Our results show that the physics of the charge trapping in HfSiON is unique and follows logarithmic dependence with time rather than usual exponential dependence. NMOS devices fabricated with HfSiON films show acceptable electrical stability for 10 years without substantial degradation of either the threshold voltage or the drive current.

引用

页码：208 / 213

页数：6

共 32 条

[1]

BREED DJ, 1974, SOLID STATE ELECTRON, V17, P1229, DOI 10.1016/0038-1101(74)90002-1

[2] CHARGE TRAPPING IN SILICON-RICH SI3N4 THIN-FILMS [J].

BUCHANAN, DA ;

ABRAM, RA ;

MORANT, MJ .

SOLID-STATE ELECTRONICS, 1987, 30 (12) :1295-1301

[3] 80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications [J].

Buchanan, DA ;

Gusev, EP ;

Cartier, E ;

Okorn-Schmidt, H ;

Rim, K ;

Gribelyuk, MA ;

Mocuta, A ;

Ajmera, A ;

Copel, M ;

Guha, S ;

Bojarczuk, N ;

Callegari, A ;

D'Emic, C ;

Kozlowski, P ;

Chan, K ;

Fleming, RJ ;

Jamison, PC ;

Brown, J ;

Arndt, R .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :223-226

[4]

CARTER RJ, 2001, INT WORKSH GAT INS, P94

[5] Structural and electrical properties of HfO2 with top nitrogen incorporated layer [J].

Cho, HJ ;

Kang, CS ;

Onishi, K ;

Gopalan, S ;

Nieh, R ;

Choi, R ;

Krishnan, S ;

Lee, JC .

IEEE ELECTRON DEVICE LETTERS, 2002, 23 (05) :249-251

[6]

Choi CH, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P857, DOI 10.1109/IEDM.2002.1175972

[7]

DiMaria D.J., 1978, PHYSICS SIO2 ITS INT, P160

[8]

DIMARIA DJ, 1975, PHYSICAL REV B, V11

[9]

Gusev E.P., 2001, IEDM Tech. Dig, P451, DOI DOI 10.1109/IEDM.2001.979537

[10]

Hauser JR, 1998, AIP CONF PROC, V449, P235

← 1 2 3 4 →