共 13 条
[1]
Abdollahi A, 2002, ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P213, DOI 10.1109/LPE.2002.1029605
[2]
BOROS E, 2000, PSEUDO BOOLEAN OPTIM
[3]
GBUPTA A, 2000, ACM T DES AUTOMAT EL, P510
[4]
HACHTEL GD, 2000, LOGIC SYNTHESIS OPTI
[5]
A gate-level leakage power reduction method for ultra-low-power CMOS circuits
[J].
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE,
1997,
:475-478
[6]
Johnson M. C., 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), P442, DOI 10.1109/DAC.1999.781357
[8]
Naidu SR, 2001, DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, P370, DOI 10.1109/DATE.2001.915051
[9]
Rao RM, 2003, ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, P689
[10]
*SEM IND ASS, 2003 INT TECHN ROADM