Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L-GATE) below 50nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1A/cm(2) for gate leakage is overly pessimistic and that leakage values of up to 100A/cm(2) are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50nm L-GATE dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50nm L-GATE transistors are described for the first time.