High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay

被引：43

作者：

Hargrove, M ^{[1
]}

Crowder, S ^{[1
]}

Nowak, E ^{[1
]}

Logan, R ^{[1
]}

Han, LK ^{[1
]}

Ng, H ^{[1
]}

Ray, A ^{[1
]}

Sinitsky, D ^{[1
]}

Smeys, P ^{[1
]}

Guarin, F ^{[1
]}

Oberschmidt, J ^{[1
]}

Crabbé, E ^{[1
]}

Yee, D ^{[1
]}

Su, L ^{[1
]}

机构：

[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Junction, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746436

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report a high-performance CMOS operating at 1.5V with 11.9 ps nominal inverter delay at 0.06/0.08 mu m L-eff for NMOS and PMOS. Both NMOS and PMOS devices, with 3.6 nm inversion T-ox, have the best current drive reported to date at fixed I-off. Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 9.7ps inverter delay. These devices are incorporated in a 0.18 mu m technology that offers a 4.2 mu m(2) SRAM cell and dual gate oxide for interfacing to 2.5V.

引用

页码：627 / 630

页数：4

共 4 条

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