Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation

A new method is proposed for the fabrication of planar single crystal silicon nanowires down to 8 nm in diameter. In this method silicon lines are defined on silicon-on-insulator with electron beam lithography followed by a metal liftoff process and a silicon plasma etch. Low temperature oxidation is then used to shrink these lines to a sub-10 nm diameter. Normal stress generated by the expansion of the viscous oxide during oxidation eventually stops the reaction, leaving a small silicon core at the center of the line. The effect of the crystallographic orientation of the line and the stress complications caused by the substrate are investigated. (C) 1997 American Vacuum Society.