On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits

This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCC's). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples.