DESIGN AND SYNTHESIS OF SELF-CHECKING VLSI CIRCUITS

被引:107
作者
JHA, NK
WANG, SJ
机构
[1] Department of Electrical Engineering, Princeton University, Princeton
基金
美国国家科学基金会;
关键词
D O I
10.1109/43.229762
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur; thus, data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking functional circuits. In this paper, we explore methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers. The area overhead for all proposed design alternatives is studied in detail.
引用
收藏
页码:878 / 887
页数:10
相关论文
共 40 条
[1]   DESIGN OF TOTALLY SELF-CHECKING CHECK CIRCUITS FOR M-OUT-OF-N CODES [J].
ANDERSON, DA ;
METZE, G .
IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (03) :263-269
[2]  
ASHJAEE MJ, 1977, IEEE T COMPUT, V26, P737, DOI 10.1109/TC.1977.1674911
[3]   A NOTE ON ERROR DETECTION CODES FOR ASYMMETRIC CHANNELS [J].
BERGER, JM .
INFORMATION AND CONTROL, 1961, 4 (01) :68-&
[4]   SYSTEMATIC UNIDIRECTIONAL BURST DETECTING CODES [J].
BLAUM, M .
IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (04) :453-457
[5]  
BOSE B, 1985, IEEE T COMPUT, V34, P1026, DOI 10.1109/TC.1985.1676535
[6]  
BOSE B, 1986, IEEE T COMPUT, V35, P350, DOI 10.1109/TC.1986.1676768
[7]  
BRAYTON R, 1984, LOGIC MINIMIZATION A
[8]   MIS - A MULTIPLE-LEVEL LOGIC OPTIMIZATION SYSTEM [J].
BRAYTON, RK ;
RUDELL, R ;
SANGIOVANNIVINCENTELLI, A ;
WANG, AR .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (06) :1062-1081
[9]  
CARTER WC, 1968, IFIP C 68, V2, P878
[10]  
CASTILLO X, 1982, IEEE T COMPUT, V31, P658, DOI 10.1109/TC.1982.1676063