DESIGN AND SYNTHESIS OF SELF-CHECKING VLSI CIRCUITS

被引:107
作者
JHA, NK
WANG, SJ
机构
[1] Department of Electrical Engineering, Princeton University, Princeton
基金
美国国家科学基金会;
关键词
D O I
10.1109/43.229762
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur; thus, data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking functional circuits. In this paper, we explore methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers. The area overhead for all proposed design alternatives is studied in detail.
引用
收藏
页码:878 / 887
页数:10
相关论文
共 40 条
[11]   DESIGN OF A SELF-CHECKING MICROPROGRAM CONTROL [J].
COOK, RW ;
SISSON, WH ;
STOREY, TF ;
TOY, WN .
IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (03) :255-262
[12]   OPTIMAL STATE ASSIGNMENT FOR FINITE STATE MACHINES [J].
DEMICHELI, G ;
BRAYTON, RK ;
SANGIOVANNIVINCENTELLI, A .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (03) :269-285
[13]   MUSTANG - STATE ASSIGNMENT OF FINITE STATE MACHINES TARGETING MULTILEVEL LOGIC IMPLEMENTATIONS [J].
DEVADAS, S ;
MA, HK ;
NEWTON, AR ;
SANGIOVANNIVINCENTELLI, A .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (12) :1290-1300
[14]  
DIAZ M, 1974, JUN P INT S FAULT TO
[15]  
DONG H, 1982, 12TH INT S FAULT TOL, P317
[16]  
DUE X, 1991, IEEE T COMPUT AID D, V10, P28
[17]  
FRIEMAN CV, 1962, INFORM CONTR, V5, P64
[18]  
GAITANIS N, 1983, IEEE T COMPUT, V32, P273, DOI 10.1109/TC.1983.1676219
[20]  
JHA NK, 1987, 17TH INT S FAULT TOL, P96