High-density chain ferroelectric random access memory (chain FRAM)

被引：46

作者：

Takashima, D ^{[1
]}

Kunishima, I

机构：

[1] Toshiba Corp, Adv Semicond Devices Res Labs, Yokohama, Kanagawa 235, Japan

[2] Toshiba Corp, Microelect Engn Lab, Kawasaki, Kanagawa 210, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 05期

关键词：

ferroelectric memory; nonvolatile; random access memories;

D O I：

10.1109/4.668994

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F-2 size memory cell using the planar transistor so far reported, and random access, The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V-dd cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation.

引用

页码：787 / 792

页数：6