Impact of weak Fermi-level pinning on the correct interpretation of III-V MOS C-V and G-V characteristics

被引:60
作者
Martens, K.
Wang, W.
De Keersmaecker, K.
Borghs, G.
Groeseneken, G.
Maes, H.
机构
[1] IMEC, B-3001 Louvain, Belgium
[2] Katholieke Univ Leuven, Louvain, Belgium
关键词
III-V MOS capacitance; C-V interpretation; Fermi-level pinning;
D O I
10.1016/j.mee.2007.04.039
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The commonly encountered frequency dispersion and distorted behavior of GaAs and III-V MOS C-V and G-V is clarified by using MOS interface state theory. The relation of the C-V behavior with Fermi-level pinning of III-V MOS is explained. It is shown why it is difficult to quantify the interface state density using the conductance method for III-V MOS. A qualitative distinction of interface state behavior from common frequency dispersion due to series resistance is also put forward and guidelines are given to properly interpret III-V admittance data.
引用
收藏
页码:2146 / 2149
页数:4
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