VLSI implementation of 350MHz 0.35μm 8 bit merged squarer

被引：46

作者：

Kolagotla, RK ^{[1
]}

Griesbach, WR ^{[1
]}

Srinivas, HR ^{[1
]}

机构：

[1] Lucent Technol, Allentown, PA 18103 USA

来源：

ELECTRONICS LETTERS | 1998年 / 34卷 / 01期

关键词：

D O I：

10.1049/el:19980057

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The partial-products of a squarer are symmetric about the diagonal and are typically folded and shifted to reduce the depth of the array. The authors describe a technique that further reduces the critical path by merging the partial-products along the diagonal with the rest of the folded array. An 8 bit squarer operates at 350MHz in the Lucent 0.35 mu CMOS process.

引用

页码：47 / 48

页数：2