The era of low power microelectronics began with the invention of the transistor in the late 1940's and came of age with the invention of the integrated circuit in the late 1950's. Historically, the most demanding applications of low power microelectronics have been battery operated products such as wrist watches, hearing aids, implantable cardiac pacemakers, pocket calculators, pagers, cellular telephones and prospectively the hand-held multi-media terminal. However, in the early 1990's low power microelectronics rapidly evolved from a substantial tributary to the mainstream of microelectronics. The principal reasons for this transformation were the increasing packing density of transistors and increasing clock frequencies of CMOS microchips pushing heal removal and power distribution to the forefront of the problems confronting the advance of microelectronics. The distinctive thesis of this discussion is that future opportunities for low power gigascale integration (GSI) will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: 1) fundamental 2) material, 3) device, 4) circuit, and 5) system. The three most important fundamental limits on low power GSI are derived from the basic physical principles of thermodynamics, quantum mechanics, and electromagnetics. The key semiconductor material limits are determined by carrier mobility, carrier saturation velocity, breakdown field strength and thermal conductivity: and the prime material limit of an interconnect is imposed by the relative dielectric constant of its insulator. The most important device limit is the minimum channel length of a MOSFET, which in turn determines its minimum switching energy and intrinsic switching time. Channel lengths below 60 nm for bulk MOSFET's and below 30 nm for dual gate SOI MOSFET's are projected. Response time of a canonical distributed resistance-capacitance network is the principal device limit on interconnect performance. To insure logic level restoration in static CMOS circuits, a minimum allowable supply voltage is about 4KT/q. For a conservative 0.1 mu m CMOS technology and 1.0 V supply voltage, the minimum switching energy of a ring oscillator stage is about 0.1 fJ and the corresponding delay time is less than 5.0 ps. Five generic system limits are set by: 1) the architecture of a chip, 2) the power-delay product of the CMOS and interconnect technology used to implement the chip, 3) the heat removal or cooling capacity of the packaging technology, 4) the cycle time requirements imposed on the chip and 5) its physical size. To date, all microchips have been designed to dissipate the entire amount of electrical energy transferred during a binary switching transition. However, new approaches based on the second law of thermodynamics point the way to recycle switching energy by avoiding the erasure of information and switching under quasi-equilibrium conditions. Adiabatic computing technology offers promise of significant new advances in low power microelectronics. Practical limits are elegantly summarized by Moore's Law which defines the exponential rate of increase with time of the number of transistors per chip. One billion transistor chips are projected for the year 2000 and 100 billion transistor chips ave projected before 2020 by joining the results of the analyses of theoretical and practical limits through definition of the chip performance index as the quotient of the number of transistors per chip and the power delay product of the corresponding technology.
