THERMAL-PROPERTIES OF POWER HBTS

Simulations of the thermal behavior of AIGaAs/ GaAs HBT power transistors have been carried out to establish the quantitative tradeoff between power density, chip layout and junction temperatures. Numerical programs were used to model different aspects of HBT thermal behavior. These programs provide a dynamic solution for temperature distribution using a three-dimensional model which is very general in its ability to model composite chip cross sections. A model was developed to calculate threshold power densities for thermal instability. Standard and novel methods of controlling maximum temperatures in the devices are explored and evaluated. These methods include ''Flip Chip'' bonding and the use of Partial Vias. The prevention of thermal instability is described. The thermal time constants are found to have a fast component, on order of a few microseconds, and a slower component that depends on substrate thickness.