LARGE AREA SILICON ON INSULATOR BY DOUBLE-MERGED EPITAXIAL LATERAL OVERGROWTH

被引:7
作者
SUBRAMANIAN, CK
NEUDECK, GW
机构
来源
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 1992年 / 10卷 / 02期
关键词
D O I
10.1116/1.586425
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The process and feasibility verification for a full wafer silicon-on-insulator (SOI) process by using two merged epitaxial lateral overgrowths has been achieved. This process can be used to produce SOI material with a wide range of silicon thicknesses from 0.1-mu-m to several microns thick and is compatible with three-dimensional circuit integration. Formation of local area SOI islands, formation of vertical wall seed windows, and epitaxial lateral overgrowth from these narrow vertical seeds have been demonstrated. This SOI process has the potential to reduce the defect density and cost of SOI substrates.
引用
收藏
页码:643 / 647
页数:5
相关论文
共 6 条
[1]  
GILBERT PV, 1990, SILICON SELECTIVE EP
[2]  
JASTRZEBSKI L, 1989, J ELECTROCHEM SO NOV, V136
[3]  
SHAHIDI G, 1990, IEDM P DEC
[4]  
VASUDEV K, 1990, SOLID STATE TECH NOV, V61
[5]   3-DIMENSIONAL STACKED MOS-TRANSISTORS BY LOCALIZED SILICON EPITAXIAL OVERGROWTH [J].
ZINGG, RP ;
FRIEDRICH, JA ;
NEUDECK, GW ;
HOFFLINGER, B .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1990, 37 (06) :1452-1461
[6]  
1983, J CRYST GROWTH OCT, V63