HYBRID-11 GBIT/S PARALLEL PROCESSING DECISION CIRCUIT USING SUBMICRON SILICON BIPOLAR ICS

被引：5

作者：

RUNGE, K ^{[1
]}

YOUNG, J ^{[1
]}

BAGHERI, M ^{[1
]}

MILLICKER, D ^{[1
]}

KIPNIS, I ^{[1
]}

SNAPP, C ^{[1
]}

机构：

[1] AVANTEK INC,NEWARK,CA 94560

来源：

ELECTRONICS LETTERS | 1990年 / 26卷 / 17期

关键词：

Bipolar devices; Silicon;

D O I：

10.1049/el:19900901

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design and implementation of a submicron-silicon bipolar parallel processing master-slave D-type flip-flop decision circuit, operating at data rates as high as HGbit/s is described. This is the fastest reported decision circuit for silicon bipolar technology. The ICs used in the hybrid circuit were fabricated using a 0-6/an, non-polysilicon emitter technology, and mounted in a package employing coplanar waveguides. © 1990, The Institution of Electrical Engineers. All rights reserved.

引用

页码：1402 / 1404

页数：3

共 7 条

[1] BAGHERI M, 1989, P IEEE BIPOLAR CIRCU
[2] CLAWIN D, 1985, IEEE INT SOL STAT CI, P222
[3] LEUNG CC, 1988, MICROWAVES RF, P232
[4] NAKAGAWA K, 1990, P OPTICAL FIBER C SA
[5] 11 GBIT/S, 260KM TRANSMISSION EXPERIMENT USING A DIRECTLY-MODULATED 1536NM DFB LASER WITH 2 ER-DOPED FIBER AMPLIFIERS AND CLOCK RECOVERY
RIGHETTI, A
FONTANA, F
DELROSSO, G
GRASSO, G
IQBAL, MZ
GIMLETT, JL
STANDLEY, RD
YOUNG, J
CHEUNG, NK
TARBOX, EJ
[J]. ELECTRONICS LETTERS, 1990, 26 (05) : 330 - 332
[6] SUB-MICRON SILICON BIPOLAR MASTER-SLAVE D-TYPE FLIP-FLOP FOR USE AS 8-1 GBIT/S DECISION CIRCUIT AND 11-2 GBIT/S DEMULTIPLEXER
RUNGE, K
GIMLETT, JL
CLAWIN, D
WAY, W
CHEUNG, NK
KIPNIS, I
SNAPP, C
[J]. ELECTRONICS LETTERS, 1989, 25 (20) : 1346 - 1347
[7] SUZUKI M, 1984, IEEE J SOLID STATE C, V19

← 1 →