THE TORUS ROUTING CHIP

被引:341
作者
DALLY, WJ
SEITZ, CL
机构
[1] California Inst of Technology,, Pasadena, CA, USA, California Inst of Technology, Pasadena, CA, USA
关键词
INTEGRATED CIRCUITS; VLSI; -; Applications;
D O I
10.1007/BF01660031
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The torus routing chip (TRC) is a self-timed VLSI chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels. A prototype TRC with byte-wide self-timed communication channels achieved on first silicon a throughput of 64 Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only 150 ns per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.
引用
收藏
页码:187 / 196
页数:10
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