A SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION

被引:19
作者
ISHITANI, T
TANSHO, K
MIYAHARA, N
KUBOTA, S
KATO, S
机构
关键词
D O I
10.1109/JSSC.1987.1052775
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
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页码:575 / 582
页数:8
相关论文
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